Package outlines review and useful links

Who publishes standards for package outlines of IC, semiconductors and passive components?

In this article we present world organisations for publishing IC (Integrated Circuit) and discrete semiconductor package outlines standards. These organisations publish many standards but our focus is on package outline types and their dimensions. List of organisations are:

JEDEC (Solid State Technology Association)

JEDEC (Joint Electronic Device Engineering Councils) is international standards organization that prepares and publishes International Standards for electrical and electronic technologies. JEDEC published many of popular package outline drawings for IC, semiconductors and other electronic parts. All of this standard packages are described in part JEP-95. Some of these standards are listed below:

Standard Package outlines of DO (Diode Outline):

  • DO-015 (Diode Axial Through Hole)
  • DO-035 (Diode Axial Through Hole)
  • DO-041 (Diode Axial Through Hole)
  • DO-213 (Diode Melf)
  • DO-214 (Diode Molded – “J” leads)
  • DO-215 (Diode Molded – gullwing leads)

Standard Package outlines of MO (Microelectronic Outline):

  • MO-047 (PLCC (Plastic Chip Carrier)1.27mm Pitch, Square Type)
  • MO-118 (SOP (Shrink Small Outline Package)0.635mm (0.025″) Pitch, .300″ Body Width)
  • MO-119 (SOP (Plastic Small Outline Package) 1.27mm (0.05″) Pitch, .300″ Body Width)
  • MO-120 (SOP (Plastic Small Outline Package) 1.27mm (0.05″) Pitch, .350″ Body Width)
  • MO-137 (SOP (Plastic Shrink Small Outline Package) 0.635mm (0.025″) Pitch, .150″ Body Width)
  • MO-142 (TSSOP (Plastic Thin Shrink Small Outline Packages ) 0.5mm Pitch, 1.2mm Max Height)
  • MO-150 (SOP (Plastic Shrink Small Outline Package) 0.65mm Pitch, 5.3mm Body Width, 2mm Max Height)
  • MO-153 (TSSOP (Plastic Thin Shrink Small Outline Package) 1.2mm Max Height)
  • MO-169 (D2PAK (Header Family Surface Mounted Peripheral Terminals))
  • MO-178 (SOT/SOP (Plastic Small Outline Transistor/Package) SOT23-5, SOT23-6, SOT23-8)
  • MO-187 (SOP (Plastic Small Outline Package)0.5mm and 0.65mm Pitch)
  • MO-193 (SOT/SOP (Plastic Thin Shrink Small Outline Transistor/Package) SOT23-5, SOT23-6, SOT23-8)
  • MO-194 (TSSOP/HTSSOP (Plastic Thin Shrink Small Outline Package with Exposed Thermal Pad) 0.4mm Pitch, 1.2mm Max Height)
  • MO-203 (Shrink SOT (Plastic Thin Shrink Small Outline Transistor))
  • MO-220 (PQFN (Plastic Quad Flat No Lead))
  • MO-229 (F-PSON (Fine Pitch Small Outline No Lead Package))
  • MO-271 (SOP (Plastic Small Outline Package) 7.62mm Body Width)

Standard Package outlines of MS (Microelectronic Standards):

  • MS-001 (PDIP (Plastic Dual Inline Package) 2.54mm (0.1″) Pitch, 6.35mm (0.25″) Body Width, 0.3″ Row Spacing, 0.53mm (0.21″) Max Height)
  • MS-010 (PDIP (Plastic Dual Inline Package) 2.54mm (0.1″) Pitch, 9.15mm (0.36″) Body Width, 0.4″ Row Spacing, 0.53mm (0.21″) Max Height)
  • MS-011 (PDIP (Plastic Dual Inline Package) 2.54mm (0.1″) Pitch, 12.7mm (0.50″) Body Width, 0.6″ Row Spacing, 0.635mm (0.25″) Max Height)
  • MS-012 (SOIC (Plastic Small Outline Integrated Circuit) 1.27mm (0.05″) Pitch, 3.9mm (0.150″) Body Width)
  • MS-013 (SOIC (Plastic Small Outline Integrated Circuit) 1.27mm (0.05″) Pitch, 7.5mm (0.300″) Body Width)
  • MS-016 (PCC (Plastic Chip Carrier) Rectangular Type, 1.27mm (0.05″) Pitch)
  • MS-019 (PDIP (Plastic Dual Inline Shrink Package) 1.78mm (0.07″) Pitch, 6.4mm (0.252″) Body Width, 0.3″ Row Spacing, 0.508mm (0.2″) Max Height)
  • MS-020 (PDIP (Plastic Dual Inline Shrink Package) 1.78mm (0.07″) Pitch, 13.7mm (0.54″) Body Width, 0.6″ Row Spacing, 0.508mm (0.2″) Max Height)
  • MS-021 (PDIP (Plastic Dual Inline Shrink Package) 1.78mm (0.07″) Pitch, 17mm (0.67″) Body Width, 0.75″ Row Spacing, 0.508mm (0.2″) Max Height)
  • MS-022 (PQFP (Plastic Quad Flat Package), 0.65mm, 0.8mm and 1mm Pitch)
  • MS-024 (TSOP (Thin Small Outline Packages) 10.16mm Body Width, 1.2mm Max Height)
  • MS-025 (TSOPII (Thin Small Outline Packages Type II) 7.62mm Body Width, 1.2mm Max Height)
  • MS-026 (PTQFP (Plastic Thin Quad Flat Package) 1.2mm Max Height)
  • MS-029 (PSQFP (Plastic Shrink Quad Flat Package) 0.4mm and 0.5mm Pitch)

 Standard Package outlines of TO (Transistor Outline):

  • TO-126 (Flat Lead .090″ Lead spacing)
  • TO-204 (Flange-Mounted Header Family .430″ Lead Spacing)
  • TO-220 (Flange-Mounted Header Family .100″ Lead Spacing)
  • TO-226 (TO-92 Header Family Flat Index)
  • TO-236 (SOT/SOP Plastic Small Outline Transistor/Package SOT23-3)
  • TO-243 (SOT89 Header Family Peripheral Terminals)
  • TO-247 (Flange-Mounted Header Family .215″ and .219″ Lead Spacing)
  • TO-251 (Flange-Mounted Family Insertion Mount .090″ Lead Spacing)
  • TO-252 (DPAK Flange Mounted Family Surface Mount)
  • TO-253 (SOT/SOP Small Outline Transistor/Package – 4 Leads, SOT143, SOT343)
  • TO-261 (SOT/SOP Plastic Small Outline Transistor/Package SOT223-3, SOT223-4)
  • TO-262 (Flange-Mounted Header Family .100″ Lead Spacing)
  • TO-263 (D2PAK Plastic Surface Mounted Header Family)
  • TO-273 (Plastic Flange-Mounted Package, 3 Leads, 2.55mm Lead Spacing)

IEC (International Electrotechnical Commission)

IEC is international standards organization that publishes and prepares International Standards in field of electronic, electrical, and similar technologies.

JEITA (Japan Electronics and Information Technology Industries Association)

JEITA is Japanese electronics trade organization. It consists of two Japanese organizations EIAJ (Electronic Industries Association of Japan) and JEIDA (Japan Electronic Industry Development Association). Some of JEITA package outline standards are listed below:

  • EIAJ_ED-7303 (describes name and code for IC packages)
  • EIAJ ED-7311-18 (P-ILGA (Plastic Interstitial Land Grid Array))
  • EIAJ ED-7311-21 (P-HSOP (Plastic Small Outline Package with Heat Sink))
  • EIAJ ED-7500A (TC-1 to TC-19, TB-1 to TB-30 and SC-1 to SC-88)
  • EIAJ ED-7500A-1 (SC-89, SC-90, SC-90/A, SC-91, SC-91A, SC-92, SC-93, SC-94, SC-95, SC-96, SC-97, SC-98, SC-98AA, SC-98AB, SC-99, SC-99A, SC-100, SC-100A, SC-100B, SC-101, SC-102 and SC-103)
  • EIAJ ED-7500A-2 (SC-104A, SC-104B, SC-105AA, SC-105AB, SC-105B, SC-106A, SC-106B, SC-106C, SC-106D, SC-107A, SC-107BA and SC-107BB)

Where can I find links of package outlines by their manufacturers?

Many manufacturers of IC, semiconductor and passive components use package outline types and their dimensions according to JEDEC, IEC and JEITA organisations but they also have products in some non standard package outlines. Useful links of standard and non standard package outlines by manufacturer are shown below:

Analog Devices, Inc. (ADI)

Atmel

Cirrus Logic

Cypress

Diodes Inc.

Fairchild Semiconductor

Maxim

Micrel

Microchip

Monolithic Power Systems

NXP

Linear Technology

ON Semiconductor

Texas Instruments

Xilinx